* H. Peter Anvin <[email protected]> wrote:
> Ingo Molnar wrote:
>> * Venki Pallipadi <[email protected]> wrote:
>>
>>> Aviod TLB flush IPIs during C3 states by voluntary leave_mm() before
>>> entering C3.
>>>
>>> The performance impact of TLB flush on C3 should not be significant with
>>> respect to C3 wakeup latency. Also, CPUs tend to flush TLB in hardware
>>> while in C3 anyways.
>>>
>
> Are there any CPUs around which *don't* flush the TLB across C3? (I
> guess it's not guaranteed by the spec, though, and as TLBs grow larger
> there might be incentive to keep them online.)
i dont think it's required for C3 to even turn off any portion of the
CPU - if an interrupt arrives after the C3 sequence is initiated but
just before dirty cachelines have been flushed then the CPU can just
return without touching anything (such as the TLB) - right? So i dont
think there's any implicit guarantee of TLB flushing (nor should there
be), but in practice, a good C3 sequence would (statistically) turn off
large portions of the CPU and hence the TLB as well.
Ingo
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[Index of Archives]
[Kernel Newbies]
[Netfilter]
[Bugtraq]
[Photo]
[Stuff]
[Gimp]
[Yosemite News]
[MIPS Linux]
[ARM Linux]
[Linux Security]
[Linux RAID]
[Video 4 Linux]
[Linux for the blind]
[Linux Resources]
