Ingo Molnar wrote:
* Venki Pallipadi <[email protected]> wrote:
Aviod TLB flush IPIs during C3 states by voluntary leave_mm() before
entering C3.
The performance impact of TLB flush on C3 should not be significant
with respect to C3 wakeup latency. Also, CPUs tend to flush TLB in
hardware while in C3 anyways.
Are there any CPUs around which *don't* flush the TLB across C3? (I
guess it's not guaranteed by the spec, though, and as TLBs grow larger
there might be incentive to keep them online.)
-hpa
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