Ingo Molnar wrote:
i dont think it's required for C3 to even turn off any portion of the
CPU - if an interrupt arrives after the C3 sequence is initiated but
just before dirty cachelines have been flushed then the CPU can just
return without touching anything (such as the TLB) - right? So i dont
think there's any implicit guarantee of TLB flushing (nor should there
be), but in practice, a good C3 sequence would (statistically) turn off
large portions of the CPU and hence the TLB as well.
I think C3 guarantees that the cache contents stay intact, and thus it
might make sense in some technology to preserve the TLB as well (being a
kind of cache.)
Otherwise, what you say here of course is absolutely correct.
-hpa
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