However, they have to do all the work of processing the memory
transation that the MSI is on the PCI bus, I don't think they
would go
so far out of their way to reorder things even if they converted the
MSI packet into a PIN to the APIC, for example.
That would suck and not surprise me that much in fact... Take the
Apple
bridge... it's unclear at which point they actually decode the MSI and
HT interrupts (the later are just internally converted to MSI-like
stores) to turn them into toggling of MPIC lines,
That's all documented just fine.
but it probably
happens as an MMIO slave on the main xbar
Yes indeed.
and I'm not 100% certain it
provides ordering vs. the previous stores to memory as they are in the
coherent domain and the MMIO is not. I just hope very much :-)
All those DMA stores get reflected to the CPUs (the north
bridge itself doesn't keep a cache directory). All this
happens in-order. There probably _is_ a window where the
last DMA store isn't yet globally visible but the CPU
interrupt was already signaled, but the act of trying to
access that data orders it itself :-)
Because
the store queue to memory can re-order on U4.
That's only the store queue to the actual memory devices,
it's outside of the coherent domain anyway.
Segher
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[Index of Archives]
[Kernel Newbies]
[Netfilter]
[Bugtraq]
[Photo]
[Stuff]
[Gimp]
[Yosemite News]
[MIPS Linux]
[ARM Linux]
[Linux Security]
[Linux RAID]
[Video 4 Linux]
[Linux for the blind]
[Linux Resources]