> If you take an INTX interrupt, it's over a pin on the motherboard and
> thus can arrive before the DMA makes it to main memory, so you have to
> have all of this fixup logic to handle that case and you don't even
> know the interrupt is really for you so you have to actually check
> the status block.
Out of curiosity. Are you sure there is no case of stupid bridge
converting the MSI into some APIC/whatever interrupt for the CPU
potentially before all previous DMA have been fully pushed to the
coherent domain (still in some internal store queue for example) ?
I suppose the Intel bridges get it right since they pretty much defined
them in the first place... but my experience with chipset designers is
that they have generally little regard for ordering issues (and the
impact those have on software) and no clue about anything related to
interrupt issues.
Ben.
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