On Tue, 2006-11-14 at 20:07 -0800, David Miller wrote:
> From: Benjamin Herrenschmidt <[email protected]>
> Date: Wed, 15 Nov 2006 15:01:00 +1100
>
> > Out of curiosity. Are you sure there is no case of stupid bridge
> > converting the MSI into some APIC/whatever interrupt for the CPU
> > potentially before all previous DMA have been fully pushed to the
> > coherent domain (still in some internal store queue for example) ?
>
> That would really suck, wouldn't it :)
>
> However, they have to do all the work of processing the memory
> transation that the MSI is on the PCI bus, I don't think they would go
> so far out of their way to reorder things even if they converted the
> MSI packet into a PIN to the APIC, for example.
That would suck and not surprise me that much in fact... Take the Apple
bridge... it's unclear at which point they actually decode the MSI and
HT interrupts (the later are just internally converted to MSI-like
stores) to turn them into toggling of MPIC lines, but it probably
happens as an MMIO slave on the main xbar and I'm not 100% certain it
provides ordering vs. the previous stores to memory as they are in the
coherent domain and the MMIO is not. I just hope very much :-) Because
the store queue to memory can re-order on U4.
Ben.
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