> Out of curiosity. Are you sure there is no case of stupid bridge
> converting the MSI into some APIC/whatever interrupt for the CPU
> potentially before all previous DMA have been fully pushed to the
> coherent domain (still in some internal store queue for example) ?
That's forbidden by the PCI spec:
"An MSI or MSI-X message, by virtue of being a posted memory write
(PMW) transaction, is prohibited by PCI ordering rules from
passing PMW transactions sent earlier by the function. The system
must guarantee that an interrupt service routine invoked as a
result of a given message will observe any updates performed by
PMW transactions arriving prior to that message."
which is not to say that there are no chipsets with errata in this
area. But I've never heard of such a thing...
- R.
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