James Bottomley <[email protected]> wrote:
> On Mon, 2006-09-25 at 18:39 +0100, Al Viro wrote:
> > Far more interesting question: where does the hardware expect to see
> > the
> > upper 16 bits of that 32bit value? Which one it is -
> > LmSEQ_INTEN_SAVE(lseq)
> > ori LmSEQ_INTEN_SAVE(lseq) + 2?
>
> I don't honestly know. The change was made as part of a slew of changes
> by Robert Tarte at Adaptec to make the driver run on Big Endian
> platforms. I've copied Jack Hammer who's now looking after it in the
> hope that he can enlighten us.
This was not Rob. I sent this bad code out in a roll up of support for
non-x86 systems (and bad process for not running sparse on the
patch which passed the buck onto someone else to find).
I think it might have been for an IA64 offset issue someone was seeing. I
cannot find the original mail on the issue in my mail archives.
I will try and track down a IA64 system to see if we can verify this is
really needed. If not we should revert back to the original dword
implementation.
-andmike
--
Michael Anderson
[email protected]
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