Re: increased translation cache footprint in v2.6

[Dan Malek <dan@embeddededge.com>]

On Jun 28, 2005, at 2:18 AM, Benjamin Herrenschmidt wrote:

> Can't you put the "8Mb page" flag at the PMD level and use normal 
> kernel
> page tables ? You'll have to fill PMD entries two by two but that
> shouldn't be too difficult.

Yep.  You guys are suggesting all of the things that have been tried,
some more successfully than others.  The values in the pmd are just
half of the battle, you also need plenty of code to adjust the MMU
assist registers, copy stuff out of the ptes into the pmds, and so on.

None of this is new to me, I've been working on various solutions
for quite some time.  The only thing I'm going to do different now is
separate the paths for the user and kernel TLB miss handlers.  I
just never wanted the more frequently used 4K path to pay the
overhead of these other page sizes.  In the past, I tried to write
a single, fast code path for all cases, but it just doesn't work out.

Thanks.


	-- Dan

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