Re: increased translation cache footprint in v2.6

[Dan Malek <dan@embeddededge.com>]

On Jun 26, 2005, at 3:09 PM, Marcelo Tosatti wrote:

> Thats a very interesting idea, will probably optimize performance in
> general ("why did nobody thought of it before?" kind).

I've done this before, used the pgd/pmd or pte  to hold large page
size entries.  The problem is the amount of code needed in the
tlbmiss handler to implement this.  The Linux page table structure
doesn't allow us to easily format this information, so we have lots
of code in the handler to fabricate these entries.  It's a significant
overhead for the normal 4K path that was hard to justify.

> The increase in TLB miss handler size might be offset by the reduced
> kernel misses...

We need to be optimizing the applications, since that is where the
real work is done and where the system spends most of it's time.
The kernel is easy to optimize with pinned entries, then we have the
best solution.  A minimal overhead for the 4K pages, plus an optimal
kernel mapping.

I do want the solution of variable page sizes in the kernel, because
we don't have to reserve wired entries, providing the best solution.
I'm always thinking of this and experiment with it from time to time, 
but
I haven't found a solution that is satisfactory to me :-)  Maybe 
something
like an early kernel/user test and separate code paths, but I now have
a solution that eliminates our current test, and I don't want to put it
back in :-)  My holy grail is a 4 instruction tlb miss handler, but I 
haven't
been able to get the PTEs formatted correctly so everyone is happy.


Thanks.

	-- Dan

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