Re: increased translation cache footprint in v2.6

[Dan Malek <dan@embeddededge.com>]

On Jun 26, 2005, at 8:53 PM, David S. Miller wrote:

> So that's 7 instructions, 2 instruction cache lines, with no main
> memory accesses.  Surely the PPC folks can do something similar. :-)

It's not that easy on the 8xx.  It actually implements a two level
hardware page table.  Basically, I want to load the PMD into the
first level of the hardware, then the PTE into the second level 
register.
We have to load both registers with some information, but I can't
get the control bits organized in the pmd/pte to do this easily.
There is also a fair amount of hardware assist in the MMU for
initializing these registers and providing page table offset computation
that we need to utilize.

With the right page table structure the tlb miss handler is very 
trivial.
Without it, we have to spend lots of time building the entries 
dynamically.
Because of the configurability of the address space among text, data,
IO, and uncached mapping, we simply can't test an address bit and
build a new TLB entry.  So, I want to use the existing page tables to
represent the spaces, then have the tlb miss handler just use that
information.  I'll take a closer look at the kernel/user separate code
paths again.

Thanks.

	-- Dan

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