The inline asm version has the EXACT SAME PROBLEM as the "volatile"
version has: it means that the compiler is unable to combine trivial
instructions.
This simply isn't true. The compiler *can* combine asm stuff:
typedef struct { int counter; } atomic_t;
static inline __attribute__((pure)) int atomic_read(const atomic_t *v)
{
int x;
asm("ld %0,@%1" : "=r"(x) : "r"(&v->counter), "m"(v->counter));
return x;
}
int f(atomic_t *x)
{
return atomic_read(x) + atomic_read(x);
}
int g(atomic_t *x)
{
return 0 * atomic_read(x);
}
generates
f:
ld r0,@r0
slli r0,#1
jmp lr
g:
ldi r0,#0
jmp lr
So why the *hell* you'd expect the asm version to be smaller, I can't
imagine.
I expect it to be smaller than the current code, which uses the
"big hammer" volatile version. We're talking about m32r here,
not x86. Even when using "volatile asm" it shouldn't generate
much bigger code.
Anyhow, I answered my own question: on m32r, you cannot use "m"
with ld/st insns, since autoincrement modes don't work there (the
assembler complains, at least). So you have to force the address
into a reg instead, and _that_ causes the size increase.
If the code needs barriers, the code should damn well add them.
Sure. I'm not suggesting otherwise.
Segher
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