* Andi Kleen ([email protected]) wrote:
>
> > So if, after this, we run tsc_sched_clock() with an unstable TSC, we
> > read a last_val containing the interrupt's MSB and the last_val LSB. It
> > can particularity hurt if we are around a 32 bits overflow, because time
> > could "jump" forward of about 1.43 seconds on a 3 GHz system.
> >
> > So I guess we need synchronization on the fast path, and therefore using
> > cmpxchg_local on x86_64
>
> On x86-64 the 64bit write is atomic against interrupts.
>
> You're right 32bit has a problem though. I'm not too happy about
> cmpxchg though because that wouldn't work on some CPUs.
>
Which CPUs ? 386 ? do they even have a cycle counter ?
Please have a look at my reply to this email for the x86_64 problematic
case. This problematic case also applies to i386 (non atomicity of tsc
read vs write to memory).
> I wonder if we can just get away with using a 32bit value on i386.
> Just for the purpose of keeping the value monotonic it should be good
> enough. Will think about it.
>
Yes, it could work. In this case you have to be aware that the 32 LSBs
of the TSC will overflow every ~ 1s and, in order to be sure to be able
to detect the overflow, you have to do at least 1 TSC read per second
(more precisely per 32 LSB overflow period).
> Thanks for the review.
>
YW,
Mathieu
> -Andi
>
--
Mathieu Desnoyers
Computer Engineering Ph.D. Student, Ecole Polytechnique de Montreal
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68
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