Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance

Another architecture tested

Comparison: irq enable/disable vs local CMPXCHG
             enable interrupts (STI)   disable interrupts (CLI)    local CMPXCHG
Tested-by: Mathieu Desnoyers <[email protected]>
IA32 (P4)               112                        82                       26
x86_64 AMD64            125                       102                       19
Tested-by: Alexandre Guédon <[email protected]>
x86_64 Intel Core2 Quad  21                        19                        7


-- 
Mathieu Desnoyers
Computer Engineering Ph.D. Student, Ecole Polytechnique de Montreal
OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F  BA06 3F25 A8FE 3BAE 9A68
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References:
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Andi Kleen <[email protected]>
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Christoph Lameter <[email protected]>
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Martin Bligh <[email protected]>
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Christoph Lameter <[email protected]>
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Martin Bligh <[email protected]>
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Mathieu Desnoyers <[email protected]>
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Christoph Lameter <[email protected]>
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Mathieu Desnoyers <[email protected]>
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Christoph Lameter <[email protected]>
- Re: [patch 00/10] [RFC] SLUB patches for more functionality, performance and maintenance
  - From: Mathieu Desnoyers <[email protected]>

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