On Sun, 20 May 2007 09:09:16 +0200
Thomas Gleixner <[email protected]> wrote:
> > Mr. Thomas Gleixner,
> > any idea to fix this problem?
>
> Which problem ?
The problem is CPU1 receives 38239 interrupt-16
but CPU0 receives only 15 interrupt-16
CPU0 should receive more interrupts.
CPU0 CPU1
0: 85 0 IO-APIC-edge timer
1: 0 698 IO-APIC-edge i8042
6: 0 5 IO-APIC-edge floppy
8: 0 1 IO-APIC-edge rtc
9: 0 0 IO-APIC-fasteoi acpi
12: 0 114 IO-APIC-edge i8042
14: 369 2281 IO-APIC-edge ide0
15: 0 24 IO-APIC-edge ide1
16: 15 38239 IO-APIC-fasteoi yenta, pcnet_cs <<< problem
17: 0 0 IO-APIC-fasteoi yenta
NMI: 0 0
LOC: 50548 50547
ERR: 0
MIS: 15503
Best Regards
Komuro
> On Sun, 2007-05-20 at 11:14 +0900, Komuro wrote:
> > Hi,
> >
> >
> > [clockevents: i386 drivers patch] introduces
> > irqbalance-does-not-work-properly problem.
>
> it disables irq balancing for IRQ0, but this does not affect any other
> interrupts. It is almost irrelevant as the PIT/HPET timer interrupt
> (irq0) is disabled anyway and the local apic timer is used.
>
> > > CPU0 CPU1
> > > 0: 85 0 IO-APIC-edge timer
>
> There is no interrupt happening after bootup, so balancing is not a
> problem here.
>
> > Mr. Thomas Gleixner,
> > any idea to fix this problem?
>
> Which problem ?
>
> tglx
>
>
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