From: Nick Piggin <[email protected]>
Date: Sat, 21 Oct 2006 00:39:40 +1000
> So moving the flush_cache_mm below the copy_page_range, to just
> before the flush_tlb_mm, would work then? This would make the
> race much smaller than with this patchset.
>
> But doesn't that still leave a race?
>
> What if another thread writes to cache after we have flushed it
> but before flushing the TLBs? Although we've marked the the ptes
> readonly, the CPU won't trap if the TLB is valid? There must be
> some special way for the arch to handle this, but I can't see it.
Also, it is actually the case that doing page-by-page cache flushes
can be cheaper than flush_mm_cache() on certain cpus. Very few cpus
that need this cache flushing provide a "context" based cache flush.
On cpus like the mentioned hypersparc, there is no way to do a
"context" flush of the cache, so we flush the entire multi-megabyte L2
cache. Actually, it allows to flush only "user" cache lines which
keeps the kernel cache lines in there, but still it's very expensive.
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