From: Ralf Baechle <[email protected]>
Date: Thu, 19 Oct 2006 19:13:46 +0100
> That would require changing the order of cache flush and tlb flush.
> To keep certain architectures that require a valid translation in
> the TLB the cacheflush has to be done first. Not sure if those
> architectures need a writeable mapping for dirty cachelines - I
> think hypersparc was one of them.
There just has to be "a mapping" in the TLB so that the L2 cache can
translate the virtual address to a physical one for the writeback to
main memory.
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