Ar Maw, 2006-09-19 am 20:52 -0400, ysgrifennodd Karim Yaghmour:
> a) the errata & a possible thread having an IP leading back within (not
> at the start of) the range to be replaced.
> b) the errata & replacing single instruction with single instruction of
> same size.
Intel don't distinguish. Richard's reply later in the thread answers a
lot more including what Intels architecture team said about int3 being a
specific safe case for soem reason
> I was vaguely aware of the issue on x86. Do you know if this applies the
> same on other achitectures?
I wouldn't know.
> Also, this is SMP-only, right? (Not that single UP matters for desktop
> anymore, but just checking.)
There are some uniprocessor errata but I cannot see how you could patch
code, somehow take an interrupt (or return from one) without executing a
serializing instruction, so I likewise think its SMP only.
> Any pointers to the errata?
developer.intel.com 'specification update' documents (which are always
good reading).
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