Alan Cox <[email protected]> wrote on 20/09/2006 11:44:29:
> Ar Maw, 2006-09-19 am 20:52 -0400, ysgrifennodd Karim Yaghmour:
> > a) the errata & a possible thread having an IP leading back within (not
> > at the start of) the range to be replaced.
> > b) the errata & replacing single instruction with single instruction of
> > same size.
>
> Intel don't distinguish. Richard's reply later in the thread answers a
> lot more including what Intels architecture team said about int3 being a
> specific safe case for soem reason
>
> > I was vaguely aware of the issue on x86. Do you know if this applies
the
> > same on other achitectures?
>
> I wouldn't know.
It can for another reason - score-boarding: that's where a byte being
stored assumes intermediate values due to the bits not being set
simultaneously. Generally this doesn't cause a problem because data across
processors is serialised for update by mutexes. However, when applied to
code all sorts of interesting instructions can execute before the bits
settle down. I haven't heard of this troubling Intel, but it does occur on
some current architectures.
Richard
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