Rafał Bilski wrote:
>> If I understand correctly, trouble occurs when the processor tries to
>> snoop? Would disabling (via MSR) and flushing the caches before changing
>> the frequency help in that case?
>>
>> Groeten,
>> Bart
>>
>
> CPU is VIA C3 in EBGA "Nehemiah" core 6.9.8.
> I'm using flush_cache_all(). Is there anything more powerfull?
> I'm using MSR_VIA_FCR.
> I can disable L2 cache (or at least I think so) - this doesn't help.
> I can't disable L1 cache - processor stops when I'm trying to set
> I-cache or D-cache disable bit.
Maybe you need to do something with the cache bits in CR0 as well. It
could be something like that. Hardware can be stuborn. I remember the
old Winchips (C3 predecessors) hanging when trying to disable caching of
plain ram via MCR's for instance.
--
Bart Hartgers - TUE Eindhoven - http://plasimo.phys.tue.nl/bart/contact/
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