Ar Iau, 2006-06-29 am 17:16 +0200, ysgrifennodd Bart Hartgers:
> Rafał Bilski wrote:
> > CPU is VIA C3 in EBGA "Nehemiah" core 6.9.8.
> > I'm using flush_cache_all(). Is there anything more powerfull?
> > I'm using MSR_VIA_FCR.
> > I can disable L2 cache (or at least I think so) - this doesn't help.
> > I can't disable L1 cache - processor stops when I'm trying to set
> > I-cache or D-cache disable bit.
If you can flush any cached writes to RAM before you do the changeover
and after you disabled interrupts then it ought to be sufficient to
invalidate the cache just before re-enabling everything.
The reason I make that claim is that you know nobody will be DMAing over
the pages of memory you use for the speed change itself. Might need a
little care with the stack that is all.
Alan
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