On Mon, 24 Apr 2006, Stephen Hemminger wrote:
>
> Maybe that's why it never was done in the past, too much work and historical
> baggage.
It's messy. That whole ELCR register was mis-designed: you can change the
edge/level detection with it, but since it _also_ changes the polarity of
the signal, you can't actually do so from a sw angle, and it has to match
the hardware. So you can't say "I want to treat this interrupt as level
triggered", and just set the bit ;^/
To make matters worse, I wouldn't be in the least surprised if the ELCR
register is totally ignored by many south-bridges for the internally
generated interrupts (ie devices that are embedded in the SB), since the
register really doesn't matter for them.
And it doesn't help that Intel mis-designed the edge-detection logic on
the IO-APIC. On the old i8259, if you masked an interrupt and unmasked it,
an active interrupt would always be seen as an edge, because the
edge-detection was done _after_ masking. On the IO-APIC crap, the masking
is done after edge-detection, so if you mask the APIC hardware level, and
an edge happens, you'll never ever learn of it ever again.
I'm sure other system architectures have similar problems, but it's
irritating.
Linus
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