Linus Torvalds wrote:
On Tue, 14 Mar 2006, David Howells wrote:
But that doesn't make any sense!
That would mean we that we'd've read b into d before having read the new value
of p into q, and thus before having calculated the address from which to read d
(ie: &b) - so how could we know we were supposed to read d from b and not from
a without first having read p?
Unless, of course, the smp_wmb() isn't effective, and the write to b happens
after the write to p; or the Alpha's cache isn't fully coherent.
The cache is fully coherent, but the coherency isn't _ordered_.
This is what I was referring to when I said your (David's) idea of "memory"
WRT memory consistency isn't correct -- cache coherency can be out of order.
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