David Howells writes:
> Paul Mackerras <[email protected]> wrote:
>
> > No, that's not the problem. The problem is that you can get q == &b
> > and d == 1, believe it or not. That is, you can see the new value of
> > the pointer but the old value of the thing pointed to.
>
> But that doesn't make any sense!
It certainly violates the principle of least surprise. :)
Apparently this can occur on some Alpha machines that have a
partitioned cache. Although CPU 1 sends out the updates to b and p in
the right order because of the smp_wmb(), it's possible that b and p
are present in CPU 2's cache, one in each half of the cache. If there
are a lot of updates coming in for the half containing b, but the half
containing p is quiet, it is possible for CPU 2 to see a new value of
p but an old value of b, unless you put an rmb instruction between the
two loads from memory.
I haven't heard of this being an issue on any other architecture. On
PowerPC it can't happen because the architecture specifies that a data
dependency creates an implicit read barrier.
Paul.
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