Re: first bisection results in -mm3 [was: Re: 2.6.15-mm2: reiser3 oops on suspend and more (bonus oops shot!)]

[Andi Kleen <ak@suse.de>]

john stultz <johnstul@us.ibm.com> writes:
> > bus master activity:     00000000
> > states:
> >     C1:                  type[C1] promotion[C2] demotion[--] latency[000] usage[00007790]
> >    *C2:                  type[C2] promotion[--] demotion[C1] latency[010] usage[02310093]
> 
> Hrmm. Interesting. I'm not aware of C2 causing TSC stalls. This may be
> in part why we don't disable the TSC earlier.

On the dual core athlons C1 occasionally loses some ticks (it's not a real stall) when going
in/out of HLT. Since the different cores have different HLT patterns depending on load 
that causes them to drift against slowly each other, and it adds up over longer runtime.

Instead of adding lots of ugly checking code I would just check the CPUs like I do
in x86-64 and not use the TSC if the test fails. I believe the logic currently in there 
handles all modern hardware that is 64bit capable correctly.

-Andi
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