Alan Cox wrote:
On Sad, 2005-05-14 at 00:21, Jeff Garzik wrote:
If your chipset implements the 400nS lockout in hardware it certainly
seems to make sense. Nice to know someone has put it in hardware
No, it's just mostly irrelevant under SATA.
libata is for PATA devices too.
Yes, but Ben has SATA, which is the hardware in question.
The 400nS delay which interests you so much in this thread isn't the
interesting delay. The 400nS delay isn't going away. The
udelay(10)-in-a-loop is what slows things down, and shows up on Ben's
profiles.
The best solution is to convert PIO from polling to interrupt driven, so
that we're not beating up the bus (big reason for the udelay).
The ATA registers are transmitted to the device in a single packet,
called a FIS, when the Command or Device Control register is written.
When the device updates its status, or completes a command, it sends a
FIS from device to controller, instructing the controller to update its
cached copy of the Status register.
The controller in ATA style behaviour isn't required to have the status
register valid at the point the FIS is written. It probably does but it
isn't required.
After a tiny period of time, it's required to have set the BSY bit.
Jeff
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