On Wed, 2009-09-30 at 12:03 -0400, William Case wrote: > Thanks poc; > > Then it gets confusing again! > > On Wed, 2009-09-30 at 10:53 -0430, Patrick O'Callaghan wrote: > > On Wed, 2009-09-30 at 10:55 -0400, William Case wrote: > > > > > It's the data that's stored in units of 8 bits. When addresses are > > stored then of course the same applies. When they're on the address > > lines of the memory bus, they may be in groups of 16 or 32 or 64 > > (depends on the bus design). None of this matters to you as a > > programmer. > > > Understood -- I think. Put another way, on a 64 bit machine if the > memory bus is 32 lines wide the data, or whatever, would flow with the > first 32 bits immediately followed by the second 32 bits -- right? Right. Some implementations might have a bus with two cycles per word, i.e. it's cheaper but slower. Intel has done that on occasion. > (I am trying to avoid discussing whether data flows on the rising edge > or falling edge of a clock tick etc.) Please :-) > > Note that the pedantic name for a group of 8 bits is "octet". A "byte" > > is the number of bits required to represent a character in some > > encoding. > > > > > When you say "chips" above I assume you mean cell, i.e. chip = cell = > > > 1 capacitor and 1 transistor for storage of 1 bit. > > > > A chip has a whole bunch of cells (in the millions these days). They > > aren't the same. > > Then what was Markku referring to when he said "A typical 64-bit DIMM > "stick" has eight 8-bit wide chips." The chip is one of the minute > black chips I can just barely see on a RAM stick --? That is what I > originally thought. Yes. > Markku's statement then implies that a 64 bit qword is stored in an 8 x > 8 array of cells. True? No. If a 64-bit wide DIMM has 8 chips on it you can be highly confident in saying the chips are 8 bits wide, but their depth is another matter. And the fact that the chip presents an 8-bit wide interface doesn't mean that the internal organization is in 8x8 bit arrays, though it might be. Furthermore, the 64 bits in a word will pretty much *never* be stored in a single 8x8 array. They'll be stored in a number of parallel arrays for speed of access, usually across 8 separate chips. Again: this level of detail (the array size) is essentially invisible to the programmer. > By the Way: > The definition of a 'word' seems to be all over the place. > > With Intel, the definition I have read says a 'word' is 16 bits, a > 'double word (dword)' is 32 bits, and a 'quadruple word (qword)' is 64 > bits. That's true of Intel. It's not necessarily true across all computer architectures (in fact it isn't, as I mentioned in my previous reply). > The specs for the 64 bit AMD CPU I used to have defined a 'word' as > whatever the machine said it was. In my case at the time, a 'word' > would have been 64 bits. ???? A word is normally considered to be the unit of the bus cycle of the machine (but see the above discussion of dual-cycle implementations) and coincides with the maximum addressable range of virtual memory (physical memory can be less, or even more in some cases). It usually also coincides with the size of the most common machine instructions, those these can also vary depending on the architecture. Good introductions to this stuff are Hennessy and Patterson, or Tanenbaum's Computer Organization book. > I raised the question of 'words' with my local Linux Users Group and > simply got caught in a long debate amongst them with huge digressions > that resolved nothing to my satisfaction. That's because only hardware nuts and operating system geeks really care :-) poc -- fedora-list mailing list fedora-list@xxxxxxxxxx To unsubscribe: https://www.redhat.com/mailman/listinfo/fedora-list Guidelines: http://fedoraproject.org/wiki/Communicate/MailingListGuidelines
