Re: A couple of DRAM memory stick questions ??

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Thank you Markku;

The cell arrangement of DRAM has been frustrating me for a long time
now.  Probably more because I set out to find an answer than because it
was something I needed to know.

The additional questions below simply sprung to mind as I was reading
your response and are only secondary.

On Wed, 2009-09-30 at 12:07 +0300, Markku Kolkka wrote:
> William Case kirjoitti viestissään (lähetysaika keskiviikko, 30. 
> syyskuuta 2009):
> > The second diagram shows a set of 4 X 4 arrays  -- with a
> > major disclaimer about its accuracy at the bottom.  I have
> > also seen other sites plus a couple of text books I own that
> > show the cell arrangement as a linear setup.  But only for 32
> > bit machines.  I found nothing for 64 bit DRAM.
> 
> The bit width of the CPU has no effect on the DRAM chip layout.

I know.  I only mentioned the CPU registers to avoid someone taking a
lot of time explaining the difference between SRAM and DRAM.  Perhaps
mentioning latches only confused the issue.

>  
> You simply connect enough chips in parallel to achieve the 
> desired data bus width. A typical 64-bit DIMM "stick" has eight 
> 8-bit wide chips.

I'll take that information to the bank.  To state it another way just to
make sure I've got it.  A typical physical address goes to, or points
to,  8 + 8 + 8 + 8 + 8 + 8 + 8 + 8 cells arranged side-by-side in a line
on an individual DIMM/DRAM stick. 

I suspect that by thinking of address as divided into bytes rather than
a single 64 bit word (dword, qword, -- pick your author) there is a
natural division for instructions, numbers and characters within the
'word'. Or, is there some physical reason why it is thought of as 8 +
8 ...

When you say "chips" above I assume you mean cell, i.e. chip = cell = 1
capacitor and 1 transistor for storage of 1 bit.

-- 
Regards Bill
Fedora 11, Gnome 2.26.3
Evo.2.26.3, Emacs 23.1.1

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