On Sat, May 06, 2006 at 15:48:14 +1000, David Timms <dtimms@xxxxxxxxxxxxxx> wrote: > Bruno Wolff III wrote: > >On Fri, May 05, 2006 at 08:13:05 +1000, > > David Timms <dtimms@xxxxxxxxxxxxxx> wrote: > >>I think the error correcting code is at the chipset level (the ECC ram > >>just provides the extra storage bit per byte that is needed to implement > >>the ECC code). Perhaps what is happening is the chipset detects and > > > >It's more than one bit. One bit only allows you to detect single bit > >errors. > >Typically, ECC memory allows you to correct 1 bit errors and detect 2 bit > >errors. > But I'd still contend that ECC memory is only another bit per byte of > storage (or 9 chips instead of 8), and the memory itself knows not what > it is being used for. I responded to your personal copy of the message, but for the group benefit I will respond here too. You are right about the amount of memory. For ECC checking the check is done on 4 or 8 byte groups so that there are multiple extra nits available for doing single bit correction. There is more information on parity and ECC memory at: http://www.pcguide.com/ref/ram/err_Parity.htm
