On Fri, May 05, 2006 at 08:13:05 +1000, David Timms <dtimms@xxxxxxxxxxxxxx> wrote: > > I think the error correcting code is at the chipset level (the ECC ram > just provides the extra storage bit per byte that is needed to implement > the ECC code). Perhaps what is happening is the chipset detects and It's more than one bit. One bit only allows you to detect single bit errors. Typically, ECC memory allows you to correct 1 bit errors and detect 2 bit errors.
