On Sat, 2004-12-11 at 13:19 +0800, Wilson Woon wrote: Your makefile is variable intensive. When first starting out writing makefiles, do *not* use a lot of variables - you significantly increase the likelyhood of making basic errors. Rewrite the makefile without using variables. Once it works then write a makefile using variables. In this case, your error is that you made gcc one of the target files to be compiled. Best regards Marvin Dickens > Hi all... > > I have problem creating Makefile to compile my C program files. I have > two .c and one .h files. Here's my Makefile.. > > # use "gcc" to compile source files. > CC = gcc > # the linker is also "gcc". It might be something else with other compilers. > LD = gcc > # Compiler flags go here. > CFLAGS = -g -Wall > # Linker flags go here. Currently there aren't any, but if we'll switch to > # code optimization, we might add "-s" here to strip debug info and symbols. > LDFLAGS = > # use this command to erase files. > RM = /bin/rm -f > # list of generated object files. > OBJS = main.o action.o > # program executable file name. > PROG = result > > # top-level rule, to compile everything. > all: $(PROG) > > # rule to link the program > $(PROG): $(OBJS) \ > $(LD) $(OBJS) -o $(PROG) > > # now comes a meta-rule for compiling any "C" source file. > %.o: %.c \ > $(CC) $(CFLAGS) -c $< > > # rule for cleaning re-compilable files. > clean: \ > $(RM) $(PROG) $(OBJS) > > The main.c and action.c files compiled successfully. However the > result execution file failed with make: *** No rule to make target > `gcc', needed by `main.o'. Stop. error message. > > Can anyone help me? > > Thank you >
