Re: Is the PCI clock within the spec?

["linux-os (Dick Johnson)" <linux-os@analogic.com>]

On Tue, 4 Dec 2007, John Sigler wrote:

> Hello Sébastien,
>
> Sébastien Dugué wrote:
>
>> John Sigler wrote:
>>
>>> I have an x86 system, running Linux 2.6.22.1-rt9, in which I plug one
>>> or two PCI I/O boards. I had been experiencing complete system lock-ups
>>> until I sent the system to the board manufacturer, and he fixed the
>>> problem. However, he told me that the PCI clock seemed out of spec,
>>> as far as voltage is concerned.
>>>
>>> (Disclaimer: my knowledge of PCI is 0.)
>>>
>>> The board manufacturer sent me the plot of (what appears to be) voltage
>>> versus time for the PCI clock.
>>>
>>> http://linux.kernel.free.fr/plot1.jpg
>>>
>>> The system manufacturer sent me a similar plot.
>>>
>>> http://linux.kernel.free.fr/plot2.jpg
>>
>> Why did they send you those plots? What was their point?
>
> The board manufacturer originally thought that the voltage under-
> and overshot might be responsible for the system lock-ups we were
> experiencing. They sent us the first plot to document the problem.
> (In the end, the lock-up was linked to a bug in their DMA engine.)
> I asked the system manufacturer whether they could reproduce the
> voltage issue, and they sent me the second plot.
>
>>> As far as my understanding goes, the signal should alternate between
>>> 0 V and 3.3 V (??).
>>
>>   Yep, that's the idealized 3.3V signaling case. However, it looks like
>> the signal is overshooting a bit (-0.8V below 0 and +0.8V over 3.3V from looking
>> at the 1st plot) which may be due to incorrect impedance matching on the bus,
>> probes artifacts, ...
>>
>>> In the second plot, it looks like Vmax ~ 4.6V
>>> and Vmin ~ -1.4V (Pk-Pk(C1)=6.08V might mean peak-to-peak voltage?)
>>
>>   This one looks a bit high (if they measured the same voltages I wonder
>> where they got their scopes calibrated ;-) )
>
> The first plot was obtained on my system. The second plot was obtained
> on a different system, presumably identical to mine, but I don't know
> for sure.
>
>>> 0) What is this C1 both plots mention?
>>
>>   Scope Channel 1
>>
>>> 1) Am I reading the plot correctly?
>>
>>   Yep
>>
>>> 2) Is -1.4V in DC even possible?
>>
>>   Why not!
>
> Errr... I need to think about it :-)
>
>>> 3) 4.6V is 1.3V above 3.3V and -1.4V is -1.4V below 0. (Assuming I read
>>> the numbers correctly) Are these values within the PCI spec? Or are
>>> these voltages dangerous and / or might cause some problems with some
>>> PCI boards?
>>
>>   Well it depends on which of the plot is lying. Looking at the PCI spec
>> (4.2.2.1) the Vih max for a device is Vcc-max+0.5 = 3.6 + 0.5 = 4.1V
>> the Vil min is -0.5V so in this case it looks a bit high. But I would not
>> worry too much, those are only the overshoots, and the circuits have
>> clamping diodes on their inputs.
>>
>>   The test waveform voltages for the maximum ratings (4.2.2.3) against which
>> every PCI device should be qualified are higher than what you have here: 7.1V
>> peak-to-peak.
>
> OK. I suppose I should not worry then :-)
>
>>   Hope this helps.
>
> Very much! Thanks.
>
> Regards.
>

You can't just touch a scope-probe to the PCI
clock pin and clip the scope-probe grounding
lead to a convenient "ground" to make these
measurements! You need a special fixture that
will make a low-inductance connection to the
PCI bus in the same manner as the interface chip.

A scope probe will allow you to see if there is
a clock signal. That's all. You can't determine
its quality. A 4-inch ground lead on the scope
probe will result in 10-20% overshoot and undershoot
being observed.

Cheers,
Dick Johnson
Penguin : Linux version 2.6.22.1 on an i686 machine (5588.27 BogoMips).
My book : http://www.AbominableFirebug.com/
_

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