Hi,
> >and it seems like this patch and perfmon2 are going to have to
> >live with
> >each other... since they both require the use of the DS save area...
>
> Hmmm, this might require some synchronization between those two.
>
> Do you know how (accesses to) MSR's are managed by the kernel?
There is a simple MSR allocator in the nmi watchdog code. It is very
simple though and was only intended for performance counters originally
so you might need to enhance it first for complicated things.
I agree it needs to be extended to manage other not necessarily contiguous
MSR registers.
As for BTS, I am happy to see this resource exposed for debugging purposes.
Note that it could also be used for performance monitoring purposes and it
could be exploited by the perfmon2 subsystem via a new sampling format. This
way one could for instance figure out the path that led to a cache miss. Of
course, this requires that some filtering be applied to BTS which today does
not differentiate loop vs. function branches, AFAIR. The current cost can
be mitigated by using a long sampling period and by monitoring longer.
--
-Stephane
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