On Monday, October 29, 2007 12:52 pm Dave Airlie wrote:
> > In this case, we're performing basically a
> > dma_sync*(...DMA_TO_DEVICE) right? Can we be sure that a single
> > flush is sufficient? Is there any window between when we flush and
> > when we start accessing memory with the device that we could get
> > into more caching trouble?
>
> Not that I can think off, but I don't work for the company who
> screwed up the coherency :-), and I don't have the docs, so please
> investigate for me ;-)
It *looks* like it'll be enough. I assume Keith has talked to the
chipset guys to confirm this.
> > Looks reasonable, I'm not sure we can do much better. The only
> > concern I have is that allocating some more PCI space like that may
> > end up clobbering some *other* hidden BIOS mapping, but there's not
> > a whole lot we can do about that.
>
> Again I'm trying to workaround broken BIOS.. nothing I can do.
Right, BIOSes are so much fun to deal with. One other thing: it looks
like the flush mmio space has to be allocated above the top of DRAM but
below 4G. I wonder if there's an easy way to guarantee this with the
pci_bus* routines...
Jesse
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