>
> In this case, we're performing basically a dma_sync*(...DMA_TO_DEVICE)
> right? Can we be sure that a single flush is sufficient? Is there any
> window between when we flush and when we start accessing memory with
> the device that we could get into more caching trouble?
Not that I can think off, but I don't work for the company who screwed up
the coherency :-), and I don't have the docs, so please investigate for me
;-)
> Looks reasonable, I'm not sure we can do much better. The only concern
> I have is that allocating some more PCI space like that may end up
> clobbering some *other* hidden BIOS mapping, but there's not a whole
> lot we can do about that.
Again I'm trying to workaround broken BIOS.. nothing I can do.
Dave.
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