Hi,
From: Linus Torvalds <[email protected]>
> On Wed, 3 Oct 2007, Pekka Enberg wrote:
> >
> > On 10/3/07, Linus Torvalds <[email protected]> wrote:
> > > I would bet that the reason the intel-optimized memcpy triggers this is
> > > that the non-temporal stores just means that you go out directly on the
> > > bus, and it probably just shows a weakness in the chipset or bus that
> > > doesn't show with the normal cacheline accesses.
> >
> > But that should show up with memtest too, no?
>
> Not unless memtest uses non-temporal stores with the same (or similar)
> access patterns.
>
> The thing is, the CPU cache hides a *lot* of activity from the chipset,
> and changes the access patterns radically.
>
> With normal cached accesses, you'd normally see just the "fill cacheline"
> and "write out cacheline" pattern. With movnt, you'd see non-cacheline
> accesses to memory. If the chipset was tested under mostly normal loads,
> the movnt cases have been getting a lot less coverage.
I'm not so sure whether it is chipset's bug or not.
The movnt does have the WC (write combining) semantics and
bypass the hardware cache to store the data.
http://www.intel.com/products/processor/manuals/index.htm
Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 1: Basic Architecture
Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3A: System Programming Guide
Thanks in advance,
Hiro
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