H. Peter Anvin wrote:
> Mathieu Desnoyers wrote:
>
>> Ok, let's have a good look at what we want:
>>
>> 1 - get a pointer to the beginning of the immediate value within the
>> instruction.
>> 2 - make sure that the immediate value, within the instruction, is
>> written to atomically wrt all CPUs, even on older architectures
>> where non aligned writes are not atomic.
>>
>>
>
> I think you'll find that even on modern architectures cross-cacheline
> writes aren't atomic.
>
Cross-cache-line, sure. But what about just not sizeof aligned? If its
enough to avoid cross-cache-line, then that's simpler.
Which is something I was going to comment on: Mathieu, you try to align
the constant itself, but you don't prevent the instruction overall from
crossing a cache line. Given how delicate all this stuff is, it seems
like a good idea to do that.
>> * 4 bytes
>> B8 + rd MOV r32, imm32 (1 byte opcode)
>> C7 /0 MOV r/m32, imm32 (2 bytes opcode)
>> (the 2 bytes opcode can be a problem)
>>
>>
>
> If gas generates the C7 opcodes by default, then that's a bug, nothing less.
>
Well, in this case, it might be preferred if it brings the constant into
alignment without explicit padding :)
J
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