Alan Cox wrote:
John Sigler wrote:
http://www.pqimemory.com/documents/domdata.pdf
PIO mode 2 is mentioned. Even DMA seems to be supported.
Or am I mistaken?
Could there be a bug in my south bridge?
Nothing there about DMA support.
cf. document's page 12.
DMACK- (DMA acknowledge)
This signal shall be used by the host in response to DMARQ to initiate
DMA transfers.
DMARQ (DMA request)
This signal, used for DMA data transfer between host and device, shall
be asserted by the device when it is ready to transfer data to or from
the host. The direction of data transfer is controlled by DIOR- and
DIOW-. This signal is used in a handshake manner with DMACK- i.e., the
device shall wait until the host asserts DMACK- before negating DMARQ,
and re-asserting DMARQ if there is more data to transfer.
This line shall be released (high impedance state) whenever the device
is not selected or is selected and no DMA command is in progress. When
enabled by DMA transfer, it shall be driven high and low by the device.
When a DMA operation is enabled, CS0- and CS1- shall not be asserted and
transfers shall be 16-bits wide.
I took the above to mean the device was designed to support DMA.
Where did I err?
The data sheet says the media can only do 4.1MB/second which is
consistent with only needing PIO2 (actually it's far slower than PIO2)
Is such a slow speed typical of DOMs sold today?
Or do DOMs sold today support DMA bus mastering, much higher interface
rates, and much higher sustained throughput?
Regards.
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