On 06/11/2007 07:58 PM, H. Peter Anvin wrote:
Rene Herman wrote:
Aligning the kernel image on 4M could gain an additional TLB entry if
the kernel image would fit in one (4M aligned) hugepage, but not in the
3M that's left after loading the kernel at 1M physical. And that stuff
about the MTRRs...
Yup. Most CPUs won't actually use a largepage for the kernel if it's
below 4 MB (2 MB with PAE, so that's what x86-64 uses.)
Oh, thanks, that's interesting. Had no idea. In those cases it would seem to
at least potentially be a serious performance issue.
Rene.
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