On Monday 16 April 2007 3:03 am, Francis Moreau wrote:
> > Good .. this is more like an IRQ question though.
>
> ...
>
> > IRQ logic on that platform must do a few things, like:
> >
> > - NR_IRQS includes the N interrupts triggered from that chip,
> > and their numbers probably fit right sometime after the
> > core set of IRQs (which might include SOC GPIO irqs);
> >
> > - You'll provide an irq_chip for this controller, and it will
> > handle the relevant irq operations (set trigger type, mask,
> > unmask etc);
> >
> > - When configuring the IRQ handler for that "same IRQ", you'll
> > set it up to use a chained handler that you provide, which
> > reads the register to see which gpio(s) triggered the IRQ,
> > maybe acks it (if just reading that register isn't enough),
> > and then calls whatever handler was instaled for that GPIO.
> >
> > If that's not familiar to you, look at arch/arm/mach-at91/gpio.c
> > or arch/arm/mach-pxa/irq.c or arch/arm/plat-omap/gpio.c or a
> > number of other similar files showing how the "toplevel" IRQ
> > logic will demux from a "one of these N GPIOs" interrupt down
> > to the handler for that particular IRQ.
> >
>
> I think I got the picture now, thanks again.
>
> Just to be sure I understand, it seems to me that your point 2) and 3)
> are 2 different approaches to do the same thing, aren't they ?
No, all of those need to be done. (Plus maybe a few more things,
I wasn't trying to be exhaustive.) That last point is what makes
the other ones take effect ... without it, the top level IRQ will
never get dispatched to the GPIO-specific IRQ.
Look at the examples I referenced.
> If so I can only implement 2) since it seems to me better than the
> last one (it better uses genirq layer).
No, implementing all of those points is required. That's how
the relevant parts of the IRQ layer connect to each other.
- Dave
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