MMIO write ordering (was Re: ieee1394: host adapter disappears on 1394 bus reset)

[Stefan Richter <stefanr@s5r6.in-berlin.de>]

I wrote:
> Question to others:
> 
> ohci1394.c::ohci_irq_handler() is taking a per-host spinlock around some
> register reads and writes, particularly:
> ...
> 	spin_lock_irqsave(&ohci->event_lock, flags);
> 	event = reg_read(ohci, OHCI1394_IntEventClear);
> 	reg_write(ohci, OHCI1394_IntEventClear, event &
> 						~OHCI1394_busReset);
> 	spin_unlock_irqrestore(&ohci->event_lock, flags);
> ...
> 	spin_lock_irqsave(&ohci->event_lock, flags);
> 	reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
> 	run_an_insane_loop_as_an_alleged_fix_for_dorky_hardware;
> 	spin_unlock_irqrestore(&ohci->event_lock, flags);
> ...
> 	spin_lock_irqsave(&ohci->event_lock, flags);
> 	reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
> 	reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
> 	spin_unlock_irqrestore(&ohci->event_lock, flags);
> 
> I think these spinlocks are totally useless 1. because
> ohci_irq_handler() is only called as the hardware interrupt servicing
> routine and 2. because they don't flush the register write operations.
> Right? Wrong? [Ohci1394's reg_write() is a writel().]

Also, what is the status of ordering guarantees --- or lack thereof ---
for writel() under Linux 2.6.16 and 2.6.18? Especially in presence of a
PCI-X to PCI bridge...
-- 
Stefan Richter
-=====-=-==- =-== ==-==
http://arcgraph.de/sr/
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