On Tue, Nov 21, 2006 at 09:17:59PM -0500, Alan Stern wrote:
> On Tue, 21 Nov 2006, Paul E. McKenney wrote:
>
> > > Things may not be quite as bad as they appear. On many architectures the
> > > store-mb-load pattern will work as expected. (In fact, I don't know which
> > > architectures it might fail on.)
> >
> > Several weak-memory-ordering CPUs. :-/
>
> Of the CPUs supported by Linux, do you know which ones will work with
> store-mb-load and which ones won't?
I have partial lists at this point. I confess to not having made
much progress porting my memory-barrier torture tests to the relevant
architectures over the past few weeks (handling the lack of synchronized
lightweight fine-grained timers being the current obstacle), but will
let people know once I have gotten the tests working on the machines
that I have access to.
I don't have access to SMP Alpha or ARM machines (or UP either, for that
matter), so won't be able to test those.
Thanx, Paul
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