[PATCH] large pci adress space in pci/probe.c for linux-2.6.18

[yadviga <yadviga@ru.mvista.com>]

This is a request from Cisco to update pci address space for 64-bit mips
Cavium Octeon.

The size returned by a 4GB or greater sized BAR register returns zero
which made the algorithm in pci_read_bases() hit a continue instead of
continuing to read the upper 32-bits of the address space. I needed to
add the code to check if it was a 64-bit memory space by checking the
relevant lower bits, in which case the lower 32-bits of the size are
0xffffffff by the way they calculate size. As far as I can tell this has
still not been fixed in the latest release of Linux which is 2.6.18. I
guess no one has
encountered such a large BAR register yet.



--- linux/drivers/pci/probe.c	Sat Nov  4 04:33:58 2006
+++ linux-2.6.18.2/drivers/pci/probe.c	Fri Nov 17 19:13:31 2006
@@ -165,8 +165,18 @@
 			l = 0;
 		if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
 			sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
-			if (!sz)
-				continue;
+			if (!sz) {
+				/* if BAR space is over 4GB we need to make sure that
+				   we don't bail out if the size is zero */
+				if ((l &
+				    (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
+				    == (PCI_BASE_ADDRESS_SPACE_MEMORY |
+				    PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+					    sz = 0xffffffff;
+				} else {
+					continue;
+				}
+			}
 			res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
 			res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
 		} else {