On Mon, 2006-11-06 at 16:17 -0500, Steven Rostedt wrote:
> On Tue, 7 Nov 2006, Benjamin Herrenschmidt wrote:
>
> > On Mon, 2006-11-06 at 07:35 -0500, Steven Rostedt wrote:
> >
> > > It is relevant. In powerpc, can one write happen before another write?
> > >
> > >
> > > x = 1;
> > > barrier(); (only compiler barrier)
> > > b = 2;
> > >
> > >
> > > And have CPU 2 see b=2 before seeing x=1?
> >
> > Yes. Definitely.
>
> OK, I see in powerpc, that spin lock calls isync. This just clears the
> pipeline. It doesn't touch the loads and stores, right?
Yes. That isync is to prevent loads to be speculated accross spin_lock,
thus leaking out of the lock by the top. In fact, it doesn't act on the
load per-se but it prevent speculative execution accross the conditional
branch in the spin_lock.
> So basically saying this:
>
> x=1;
> asm ("isync");
> b=2;
>
> Would that have the same problem too? Where another CPU can see x=1
> before seeing b=2?
Yes.
What isync provides is
a = *foo
spin_lock_loop_with_conditional_branch
isync
b = *bar
It prevents the read of b from being speculated by the CPU ahead of a
Ben.
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