> I'll check if there is any additional reordering that can occur AFTER the > PIO_WRITE_COUNT goes to zero. If so, it would be at bus level - not in > shub or routers. Unfortunately, at least in theory, the reordering can occur. For example a bridge on some card plugged into an SN slot is allowed to reorder things too. - R. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
- References:
- Ordering between PCI config space writes and MMIO reads?
- From: Roland Dreier <[email protected]>
- Re: Ordering between PCI config space writes and MMIO reads?
- From: Jeff Garzik <[email protected]>
- Re: Ordering between PCI config space writes and MMIO reads?
- From: Matthew Wilcox <[email protected]>
- Re: Ordering between PCI config space writes and MMIO reads?
- From: Roland Dreier <[email protected]>
- Re: Ordering between PCI config space writes and MMIO reads?
- From: Matthew Wilcox <[email protected]>
- Re: Ordering between PCI config space writes and MMIO reads?
- From: Jack Steiner <[email protected]>
- Ordering between PCI config space writes and MMIO reads?
- Prev by Date: Re: [openib-general] Ordering between PCI config space writes and MMIO reads?
- Next by Date: EIP Errors kernel 2.6.18 .AND hard lockup ... Revisted
- Previous by thread: Re: Ordering between PCI config space writes and MMIO reads?
- Next by thread: Re: Ordering between PCI config space writes and MMIO reads?
- Index(es):