On Fri, 2006-10-20 at 18:25 -0700, Andrew Morton wrote:
> On Fri, 20 Oct 2006 22:56:51 +0200
> Ingo Molnar <[email protected]> wrote:
>
> >
> > * Andrew Morton <[email protected]> wrote:
> >
> > > Oh. I thought the problem was that the timer stops when the CPU is
> > > idle. Maybe I misremembered. I'll try `idle=poll'.
> >
> > hm, wouldnt in that case the box not boot at all? But yeah, idle=poll
> > would be nice.
>
> idle=poll fixes it. The fan gets a bit noisy though ;)
So this is one of the boxen where C2 is actually C3 and lapic stops in
C3 mode. Probably BIOS magic.
What's the output of /proc/acpi/processor/CPU0/power ?
> Perhaps a suitable test would be to set up a PIT interrupt, do a hlt, see
> if the APIC timer counter has increased appropriately.
Yeah, but it has to be done later in the boot process. Looking into this
right now.
> I got this:
>
> [ 43.709238] TSC appears to be running slowly. Marking it as unstable
>
> How come? It also happens with HIGH_RES_TIMERS=n and NO_HZ=n. It only
> seems to happen when idle=poll is given.
Should happen always as the TSC is driven by the CPU clock and you have
CPUFREQ enabled.
> > could you also boot with apic=verbose and send us the full bootlog?
>
> http://userweb.kernel.org/~akpm/apic.txt
[ 11.515305] calibrating APIC timer ...
[ 11.618612] ..... tt1-tt2 831283
[ 11.618614] ..... mult: 35701101
[ 11.618616] ..... calibration result: 532021
[ 11.618619] ..... CPU clock speed is 1995.0325 MHz.
[ 11.618622] ..... host bus clock speed is 133.0021 MHz.
That looks reasonable. It really boils down to the lapic not working
when going idle.
tglx
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