From: Linus Torvalds <[email protected]>
Date: Fri, 20 Oct 2006 12:54:17 -0700 (PDT)
> Well, sparc always was crud. I can see the missing tlb entry, but if it's
> been turned read-only, the write-back should still work (it clearly _was_
> writable when the write that dirtied the cacheline happened).
I did some more digging, here's what I think the hardware actually
does:
1) On L2 cacheline load, the "user" and "writable" protection
bits are propagated from the TLB entry into the L2 cache
line. Access checks are done on L2 cache hit using this
cached copy of the two protection bits.
2) On L2 dirty cacheline writeback, the physical address is
obtained from the TLB
So what you guys are suggesting should probably work fine.
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