From: Linus Torvalds <[email protected]>
Date: Fri, 20 Oct 2006 08:49:35 -0700 (PDT)
> Why not do the cache flush _after_ the TLB flush? There's still a mapping,
> and never mind that it's read-only: the _mapping_ still exists, and I
> doubt any CPU will not do the writeback (the readonly bit had better
> affect the _frontend_ of the memory pipeline, but affectign the back end
> would be insane and very hard, since you can't raise a fault any more).
>
> Hmm?
You get an asynchronous fault from the L2 cache, and that's also what
happens when the TLB entry is missing during L2 writeback too. You
get a level 15 non-maskable IRQ when these asynchronous errors happen.
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