On Thu, Oct 12, 2006 at 01:35:12PM -0700, Jeremy Fitzhardinge wrote:
> John Richard Moser wrote:
> >That's a load more descriptive :D
> >
> >0.890 uS, 0.556uS/cycle, that's barely 2 cycles you know. (Pentium M)
> >PPC performs similarly, 1 cycle should be about 1uS.
> >
>
> No, you're a factor of 1000 off - these numbers show the context switch
> is around 1600-75000 cycles. And that doesn't really tell the whole
> story: if caches/TLB get flushed on context switch, then the newly
> switched-to task will bear the cost of having cold caches, which isn't
> visible in the raw context switch time.
>
> But modern x86 processors have a very quick context switch time, and I
> don't think there's much room for improvement aside from
> micro-optimisations (though that might change if the architecture grows
> a way to avoid flushing the TLB on switch).
OK, so since we've now amply worked out in this thread that TLB/cache flushing
is a real problem for context switching management, would it be possible to
smartly reorder processes on the runqueue (probably works best with many active
processes with the same/similar priority on the runqueue!) to minimize
TLB flushing needs due to less mm context differences of adjacently scheduled
processes?
(i.e. don't immediately switch from user process 1 to user process 2 and
back to 1 again, but always try to sort some kernel threads in between
to avoid excessive TLB flushing)
See also my new posting about this at
http://bhhdoa.org.au/pipermail/ck/2006-October/006442.html
Andreas Mohr
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