Re: Can context switches be faster?

[John Richard Moser <nigelenki@comcast.net>]

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Arjan van de Ven wrote:
> On Thu, 2006-10-12 at 14:25 -0400, John Richard Moser wrote:
> 
> Hi,
> 
>> So apparently most CPUs virtually address L1 cache and physically
>> address L2; but sometimes physically addressing L1 is better.. hur.
> 
> if you are interested in this I would strongly urge you to read Curt
> Schimmel's book (UNIX(R) Systems for Modern Architectures: Symmetric
> Multiprocessing and Caching for Kernel Programmers); it explains this
> and related materials really really well.
> 

That will likely be more useful when I've got more background knowledge;
right now my biggest problem is I'm inexperienced and haven't yet gotten
my 2-year compsci degree (more importantly, the associated knowledge
that goes with it), so things like compiler design are like "There's a
concept of turning stuff into trees and associating actions with virtual
registers and then turning that into real register accounting and
instructions, but I really don't know WTF it's doing."

I imagine once I get into the 4-year stuff I'll be able to digest
something like that; so I'll keep that in mind.  The '1st year compsci
student' crutch is annoying and I need to get rid of it so I don't feel
so damn crippled trying to do anything.

> 
>>   - Does the current code act on these behaviors, or just flush all
>>     cache regardless?
> 
> the cache flushing is a per architecture property. On x86, the cache
> flushing isn't needed; but a TLB flush is. Depending on your hardware
> that can be expensive as well. 
> 

Mm.  TLB flush is expensive, and pretty unavoidable unless you do stupid
things like map libc into the same address everywhere.  TLB flush
between threads in the same process is probably avoidable; aren't
threads basically processes with the same PID in something called a
thread group?  (Hmm... creative scheduling possibilities...)

> Greetings,
>     Arjan van de Ven
> 
> 

- --
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